1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
Shrinking of semiconductor devices to smaller geometries depends largely upon the lithographic techniques. For this reason, it is generally difficult to form line and space patterns which are smaller in width than the resolution limit of lithography.
To solve such a problem, a method has been proposed which involves forming sidewall patterns on the sidewalls of dummy patterns and performing an etching process using the sidewall patterns as a mask (see, for example, U.S. Pat. No. 6,063,688). For the present, this method allows line and space patterns to be formed at half of the pitch of the dummy patterns.
In forming a sidewall pattern using the usual method, a sidewall pattern in the shape of a closed loop will be formed along the entire sidewall of a dummy pattern. However, the proposed method takes no account of such a sidewall pattern in the shape of a closed loop. Therefore, no provision is made for the ends of the sidewall pattern and the regions close to the ends. It is impossible to form fine patterns for which exact and effective provisions have been made.
Thus, it is hitherto difficult to form patterns exactly and effectively and to obtain excellent semiconductor devices.